w55fxx serial flash eeprom series publication release date: august 1996 - 1 - revision a2 general description the w55fxx is a serial input/output flash eeprom series that is typically used as the memory cell of a w51300 (voice recorder controller) or the rom code emulator for the powerspeech tm series. the single voltage supply eliminates the need for an extra pump circuit during programming and erasing. features provides clk, addr, and data pins to operate with winbond powerspeech tm series 512k/1m/2m memory sizes available directly cascadable for longer duration fast frame-write operation - frame (32 bits) program cycle time: 400 m s (typ.) fast whole-chip-erase duration: 50 ms (max.) read data access time: 500 ns (max.) program/erase cycles: 10,000 (typ.) data retention: 10 years (typ.) low power consumption: - operating: 5 ma (typ.) - standby: 2 m a (typ.) pin configuration mode eop ctrl v addr data clk v 1 8 2 3 4 5 6 7 ss dd
w55fxx - 2 - pin description no. pin name i/o description 1 eop o end of process signal output 2 ctrl i enable signal for program and erase operations when mode = 0 input clock for mode counter when mode = 1 3 v ss i ground 4 addr i input clock for start adress shift-in 5 data i/o bidirectional data line 6 clk i input clock for data write-in and read-out 7 v dd i positive voltage supply 8 mode i mode select control pin block diagram addr data clk shift register /address counter decoder write-in buffer control circuit ctrl mode eop page-code cells /page-code flag /comparator output buffer core array por circuit pump circuit
w55fxx publication release date: august 1996 - 3 - revision a2 absolute maximum ratings parameter symbol condition rated value unit operating temp. t opr - 0 to +70 c storage temp. t stg - -65 to +150 c power supply v dd - v ss - -0.3 to +7.0 v input dc voltage v dc all pins -0.5 to v dd +1.0 v transient voltage (< 20 ns) v tran all pins -1.0 to v dd +1.0 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. dc characteristics (v dd = 4.5v, v ss = 0v, t a = 25 c) parameter symbol conditions limits unit min. typ. max. operating voltage v dd - 2.4 (note) 4.5 5.5 v standby current i sb all inputs = gnd data & eop open - 2 4 m a operating current i op in read mode data & eop open f osc = 1 mhz - 5 10 ma input voltage high v ih all input pins 2.0 v dd v low v il -0.3 - 0.8 v output current sink i ol v ol = 0.5v 2.5 5 - ma drive i oh v oh = 4.0v -2.5 -5 - ma input leakage current of ctrl, mode i li1 v in = 4.5v - - 4.5 m a input leakage current of data i li2 v in = 0v - - -4.5 m a note: for been working with w52900, the minimum operating voltage couldn't be less than 3.6 volt.
w55fxx - 4 - ac characteristics (v dd = 4.5v, v ss = 0v, t a = 25 c) parameter symbol conditions min. typ. max. unit mode pulse width t mp - 1 - - m s ctrl pulse width t wp page coding mode 400 - 700 m s clock frequency of addr f addr - - - 1 mhz clock frequency of clk f clk - - - 1 mhz clock frequency of ctrl f ctrl - - - 1 mhz interval between addr end & clk begin t i read/write mode 1 - - m s interval between clk & ctrl t gcc write mode 1 - - m s interval between addr & ctrl t gca page coding mode 1 - - m s interval between addressing end & block-erase begin t ae block erase mode 1 - - m s interval between mode rising edge & ctrl clock begin t mb mode selection 500 - - ns interval between ctrl clock end & mode falling edge t me mode selection 500 - - ns interval between mode falling edge & another pin active t gm - 1 - - m s data access time t ra read mode - - 500 ns data set up time t ws write mode 250 - - ns t as - 250 - - ns data hold time t rh read mode 0 - - ns t wh write mode 10 - - ns t ah - 10 - - ns programming duration t pr write mode 400 - - m s whole-chip-erase time t we whole-chip-erase mode 45 - 50 ms block-erase time t be block-erase mode 40 - 45 ms
w55fxx publication release date: august 1996 - 5 - revision a2 timing waveform t t 1/f clk data write cycle t t 1/f clk data read cycle t t 1/f addr data address shift-in cycle t t mode ctrl mode select duration 1/f t t 1/f ctrl data page-code cell read out cycle note: the duty cycle of any clock is 50%. clk rh ra wh ws me ctrl mb clk addr as ah ctrl rh ra
w55fxx - 6 - application circuits (for reference only) addr data clk ctrl eop mode w55fxx eop addr data clk ctrl mode w51300 for voice recorder applications addr data clk ctrl eop mode w55fxx eop addr data clk ctrl mode w51300 addr data clk ctrl eop mode w55fxx addr data clk ctrl eop mode w55fxx for powerspeech applications addr data clk ctrl eop mode w55fxx addr data clk w5280/ w52900 ordering information part no. memory size w55f05 512k bits w55f10 1m bits w55f20 2m bits
w55fxx publication release date: august 1996 - 7 - revision a2 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27516023 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.
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